1. Field of the Present Invention
The present invention generally relates to the field of microprocessor architecture and more particularly to an efficient design for a branch unit in a gigahertz processor to improve performance.
2. History of Related Art
Branch instructions determine the instructions that a processor or central processing unit (CPU) of a data processing system will execute following execution of the branch instruction. Branch instructions introduce complexity into the instruction fetching process that typically negatively affects the processor performance. Previous methods of minimizing the performance penalty associated with branch instructions are disclosed in U.S. Pat. No. 5,796,998 entitled Apparatus and Method for Performing Branch Target Address Calculation and Branch Prediciton [Sic] In Parallel in an Information Handling System, which is assigned to the assignee of the present invention and is incorporated by reference herein. With the advent of the extremely high speed processors (i.e., processors operating with a clock frequency that exceeds 1 GHz), it is becoming increasingly difficult to identify the branch instructions in any set of instructions retrieved from an instruction cache, extract necessary branch target information from these instructions, and provide, if necessary, an address to the instruction fetch unit if the program flow requires redirection, all within the timing constraints of the system. Therefore, it is desirable to provide a microprocessor with an instruction fetch unit that is capable of achieving these objectives without significantly increasing the size or complexity of the microprocessor.
A microprocessor, data processing system, and an associated method of executing microprocessor instructions and generating instruction fetch addresses are disclosed. The microprocessor includes an instruction fetch unit comprising and instruction fetch address register (IFAR) and an instruction processing unit (IPU). The IFAR is configured to provide an address to an instruction cache. The IPU is suitable for receiving a set of instructions from the instruction cache and for generating an instruction fetch address upon determining from the set of instructions that the program execution flow requires redirection. The IPU is adapted to determine that the program flow requires redirection if the number of branch instructions in the set of instructions for which branch instruction information must be recorded exceeds the capacity of IPU to record the branch instruction information in a single cycle. The IPU may include an address generation unit suitable for generating a set of branch target addresses corresponding to the set of received instructions and a multiplexer configured to receive as inputs the set of branch target addresses. The output of the multiplexer is provided to the instruction address fetch register. The IPU may include an address incrementer suitable for generating a next instruction address corresponding to the next sequential instruction address following the instruction address corresponding to the received set of addresses. In this embodiment, the next instruction address comprises an input to the multiplexer. The IPU may further include selector logic adapted to select the next instruction address as the output of the multiplexer if the number of branch instructions in the set of instructions for which branch instruction information must be recorded exceeds the capacity of IPU to record the branch instruction information in a single cycle and there are no prior predicted taken branches in the instruction set. Otherwise, the selector logic is adapted to select as the output of the multiplexer the branch target address of the first instruction predicted to be taken.